The Microchip PIC12F629 microcontroller is one of the smallest chips in the range and is a good starting point for 'dedicated micro' applications. It is low cost and easy to program.

Electronic circuits are often used to monitor and control equipment. This may be as simple as a sequencer for a model railway or sprinkler system, or as complex as a real-time industrial controller. Where once relays and logic gates were used, microcontrollers are now finding their way into sophisticated and 'intelligent' control.
Unfortunately for the private individual this approach is often not feasible since micro-controller development systems can be very expensive. However this article will show you how to use this device and explain most of the features of the chip.

A microcontroller is a 'computer in a chip', which has been designed specially for control purposes. As well as the central processing unit, most microcontrollers include random access data memory (RAM), and read only memory (ROM), timers and input/output lines; all in a single chip. Some also include more complex features such as analog to digital converters, serial communications channels and pulse width modulators. As is the case with all electronic technologies, microcontrollers are becoming smaller and many are now available in 'skinny DIP' or surface mount packages with less than 20 pins.
A few years back, the use of miniature microcontrollers was only feasible for large manufacturing companies producing tens of thousands of each product. The design process was slow. Firstly, the design engineers would use expensive design and modeling systems to lay out the design of the device. The designs were sent off to the chip manufacturer, who would take a few weeks (and a few thousand dollars) to make a couple of sample parts for testing.
Hopefully the first design was right, but more likely some bug would be found and this process would have to be repeated. Once the design was tested, the manufacturer would then schedule a production run of these parts.

This slow and costly process kept miniature microcontrollers out of reach for a growing sector of the market, such as small engineering firms who could not afford the large costs and long turnaround times. These firms frequently have small budgets and their products are often cost sensitive, have short production runs and need to be delivered quickly.
A few chip manufacturers realised this, and began producing miniature microcontrollers with development systems that the smaller companies could afford (a few hundred to a few thousand dollars).
This article is based on the PIC12F629 microcontroller, from Microchip Technologies, which has some features which make it ideal for the amateur developer. Microchip's PIC series of microcontrollers has created a lot of interest in the electronics development community. Not a day goes by without exchanges about PICs on international news networks like the Internet.
Unlike many micro-controllers, which have evolved from general purpose microprocessors, the PIC series were purposefully designed from scratch as small, cheap, feature-packed microcontrollers to suite both small and large scale developers. PICs have a rather novel reduced instruction set (RISC), which makes PIC code very compact and easy to learn. The simplicity of a RISC core allows the PICs to combine low power usage and high performance in small packages.
The main difference between the 12F629 and most other microcontrollers is that the program is stored in onboard EEPROM, instead of EPROM. EEPROM memory is erased electrically in a few milliseconds; EPROM typically requires a few minutes exposure to ultra-violet light. Microchip probably did this to allow new programs to be downloaded in the field.
EPROM-based reprogrammable devices are packaged in ceramic, with a quartz window to admit ultra violet light; however the 12F629 comes in the standard plastic packaging, which makes it cheap when compared with other reprogrammable micro-controllers. As a bonus, EEPROM program storage also does away with the need for an EPROM eraser.
The PIC12F629 is a CMOS device. This means it has a low power consumption, typically 2mA or less at a clock speed of 4MHz and just a few microamps in sleep mode. The 12F629 needs a 4.0 - 6.0V power supply for XT, RC and LP oscillator configurations and a 4.5 - 5.5V supply for the HS configuration.
 
PIC architecture
The heart of any computing device is its processing core. The PIC has a Harvard architecture, which uses separate memory access paths for program and data. This improves performance, as program memory access can be performed simultaneously with data memory access. Separate memory access also allows the instruction word width to be different from the data memory word width, a trick which the PIC designers have use to great effect in implementing the RISC core.
Unlike most microcontrollers, the PIC has an eight-bit wide data word and a 14-bit wide instruction word (earlier members of the family have 12-bit wide instruction words), allowing all PIC instructions to fit into a single instruction word. This means that the program code is very compact, the instructions execute faster and the design of the core is simplified dramatically. As an example, Microchip quotes 2.24 times the code density and 1.54 times the execution speed of a Motorola 68HC05 for the same oscillator frequency (4MHz).

The 14-bit PIC core needs only 35 instructions and no 'strange' addressing schemes, which simplifies programming. A PIC instruction cycle takes four oscillator cycles. PIC instructions are decoded and executed in one instruction cycle and in all case we talk about one cycles for each instruction-execution. Fetching an instruction also takes one instruction cycle.
The PIC has a pre-fetch pipeline, which allows an instruction to be executed while the next instruction is being fetched. This allows most instructions to execute in one instruction cycle; the exception being where executing the instruction causes a change in the program counter.
The next instruction in the pipeline cannot be used and an extra machine cycle is required to reload the pipeline. Examples of these include the GOTO and RETURN instructions.
The 12F629 has 1024 instruction addresses for your program and this is the space allowed for instructions and any table data.  It also has 64 locations for SRAM and 22 for special function registers.
It also has 128 bytes of EEPROM data, which lie outside the data space and are accessible via special purpose registers. The EEPROM data can be read and modified at run-time and, unlike RAM data, is retained when power is removed from the device.
The PIC devices based on the new 14-bit core support and in-circuit serial programming mode. This is particularly relevant for the 12F629 because the program is kept in EEPROM. A new program and EEPROM data can be downloaded without having to disassemble the circuit or the enclosure.
For example, I have designed a 12F629 based circuit which can operate underwater. The 12F629 can be reprogrammed without having to open and reseal the enclosure, and can even be reprogrammed underwater. The serial programming mode means the programming circuit can be kept very simple.
The PIC core has an eight-deep hardware stack, which is used to store return addresses for subroutine calls and the interrupt service routine.

Oscillator modes
The PIC12F629 can support eight different clock oscillator modes, which are selected by programming the corresponding configuration fuses. The LP, XT and HS modes cater for various frequency ranges of crystal or ceramic resonator operation, as well as external clock input. Such an oscillator is a must where accurate timing is required.

The RC mode requires only an external resistor and capacitor. The frequency of oscillation is determined by the resistor and capacitor values and, to a lesser extent, by the supply voltage and temperature. This mode cuts down costs at the expense of reduced accuracy. Microchip suggests that the resistor be kept in the range of 3k to 100k, to ensure oscillator stability and a reasonable degree of accuracy. Similarly, a capacitor value of at least 20pF is suggested.

Power-on reset
The PIC allows various power-on reset (POR) configurations. There are three parts to the POR delay circuitry.
The power-up timer (PWRT) is a fixed internal RC timer of approximately 72 milliseconds. This timer is enabled by setting the PWRTE configuration fuse.
After the PWRT has elapsed, the oscillator startup timer (OST) counts 1024 clock cycles for LP, XT and HS mode oscillators. This allows the oscillator time to settle down to guarantee oscillator stability.
The MCLR pin allows for an external reset to be applied. It is usually sufficient to hard wire this pin to Vdd and rely on the combination of the PWRT and OST to provide a clean start up. A longer delay can be applied by attaching external circuitry to the MCLR pin.
A word of caution, though. The MCLR pin may be attached directly to Vdd, but it must always be connected to ground via a resistor of at least 100 ohms. This resistor prevents a high current latch-up problem from occurring. Thankfully this problem is not shared by other pins on the device.

Power-down mode
The PIC devices support a power-down mode which shuts down the oscillator, 'putting the device to sleep'. The PIC enters the power down mode when the SLEEP instruction is executed. The primary purpose of this mode is to conserve power, though it may also be used as a delay.
The normal power consumption, typically about 2mA, is very low, but this drops to less than 10uA in SLEEP mode, which means that a small battery can keep a PIC in SLEEP mode for a couple of years. This makes the PIC suitable for number of circuits where very low power consumption is a major consideration.
Of course there isn't much point in having a PIC just sleeping. The wake-up sequence runs the OST sequence for the oscillator to stabilise (1024 oscillator cycles for LP, XT and HS mode oscillators, but immediate for RC mode oscillators) and then resumes execution at the instruction after the SLEEP instruction.
The PIC can be programmed to wake up on external interrupts and watch dog timer expiry. Unfortunately, since the internal oscillator is turned off, the timer/counter does not function and can't cause an interrupt. This restricts time based wake-ups to the watchdog timer expiry which, as mentioned below, is not entirely accurate. It does however still allow the PIC to be asleep most of the time, waking periodically to check for some condition, then going to sleep again.

Watchdog timer
Even the best designed circuits can sometimes freeze up or go a bit berserk due to power spikes, the phase of the moon or other glitches.
When this happens with desktop computers, it seems to be accepted as an annoying part of our high-tech way of life. However if a microcontroller deeply embedded in an appliance goes crazy, you end up with a washing machine stuck on 'spin' or flooding the laundry. A watchdog timer provides a mechanism to help increase the reliability of an embedded microcontroller.
The watchdog timer consists of a timer circuit which is built into the PIC's reset circuitry. This timer must be periodically cleared by executing a CLRWDT instruction. If the timer is allowed to expire, the watchdog 'bites' and resets the PIC.
The timer period is approximately 18 milliseconds. The period is set by an internal resistor and capacitor, so it is prone to minor change with temperature, voltage and manufacturing variations. The period can be lengthened up to approximately 2.3 seconds by using the prescaler available in the OPTION register.
The watchdog timer is enabled by programming the WDTE fuse in the configuration fuses. As mentioned above, the timer may also be used to wake the PIC from power-down mode.

Interrupts
The idea of an interrupt can be easily explained by an analogy. Consider that you are sitting at your desk performing some task. You have a phone, but it has a tiny indicator lamp instead of a ringer. This means that you need to periodically stop what you are doing and check whether the lamp is lit. If you don't do this often enough, you may miss a call; do it too often and you will never get any of your work done. This is analogous to polling.
Trying to write a program like this is very difficult, since the code must be peppered with regular checks for external events. This situation gets even more difficult if timing is critical.
Now replace the telephone's indicator lamp with the more familiar ringer. You can now get on with your work. When the phone rings, you can stop what you are doing, take the call, then get back to your original task. This is analogous to interrupt handling.
When the microcontroller hardware detects an interrupt condition, it saves the foreground task's current execution context on a stack, then starts executing the interrupt handler code — starting at a special location called the interrupt vector. This is location 04 in program memory. When the interrupt handler completes its task, it executes a 'return from interrupt' instruction which restores the suspended execution context and the foreground task continues as if nothing had happened. Since the hardware checks for the interrupt events, all the software writer needs to do is specify a single interrupt servicing routine and enable the appropriate interrupts.
Interrupts allow the foreground processing code to be considered separately from the background 'event handling' code. Interrupts really help to reduce the coupling between the fore ground task and the background tasks, making the code more robust and easier to understand. A bonus is that this code becomes more modular, which means that it is easier to build reusable software components.

Instruction set
Here is the Instruction-set for the PIC12F629. The letter "f" indicates a file (also called a register) from 20h to 5Fh. The letter "d" is the destination for the result of the operation and when d=0, the result will be placed in the W (working) register. If d=1 the result will be placed in the file itself.
The letter "C" = Carry flag in the Status register. "DC" = Digit Carry in the Status register. "Z" = Zero flag in the Status register.
These instructions are described in more detail in the .pdf file for PIC12F629 and on our Instruction Set page.

The PIC Instruction Set is very simple and can be mastered in a short time.  The table below shows the  PIC12F629  Instruction Set in contracted form. For more details on each instruction, see Instruction Set.

The PIC has one working register, the W register. It has many purposes and one of its simplest uses is a "carrier" file or register.
If you want to load one of the files (20h to 5F) with a value, the value is initially loaded into W. The value is called a literal and can be from 01 to 0FFh. These values are hex (hexadecimal) values. For the table of hex values from 00 to FF see:
Library (Decimal to Binary to HEX).
The value is then moved from W to the required file (this is a total of two instructions). W is also often used as a dummy register where the results of an operation are to be discarded.
The PIC's files are called data memory or 'data registers'  or 'data files.'
It is useful to identify the various operand types to understand how the instructions work. The first type are the byte-oriented operations on file registers. This is where all the 8 bits in a file are operated on. A typical instruction is:

 DECF   20h,1

These typically have two operands, referred to as f and d, where f is the file number (20h in this case) and d is the destination of the result (1 in this case).
The f operand is a seven-bit address which selects which file register is being manipulated. The d operand is a single bit which selects the destination of the result; 0 selects the W register and 1 selects the file register specified in f.
Note that the two clear instructions, CLRF and CLRW, really fall into this category although they do not have two operands. CLRF, the clear file instruction, requires only the f operand and the destination is implicitly the file register; CLRW, the clear W instruction, is effectively a CLRF instruction with the destination set to W.
The second type is the bit-oriented file register operations. These operations have two operands, f and b, a seven-bit file register address and three-bit bit address respectively. These allow any bit in the file registers to be set, cleared or tested.
The third type of operand requires a single literal byte operand. The mnemonics for all of these operations end in LW, indicating a literal value operation on the W register.
The last operand type is the 11-bit program address used by the GOTO and CALL operations.

Conditional execution
Unconditional branching is supported by the GOTO and CALL instructions. Conditional execution is supported by four instructions, DECFSZ, INCFSZ, BTFSC and BTFSS. All these instructions skip the execution of the next instruction if a certain test condition is met. For example:

   DECFSZ     test,f
   GOTO        loop2
   GOTO        Siren

Here the DECFSZ instruction is the decrement test, decrementing the "test" register and putting the result in the file itself. The letter ,f indicates the result is placed in the file. The GOTO  loop2 instruction is skipped if the result of this decrementing was not zero. In other words, the micro will normally go to the instruction below the DECFSZ unless the result of the file is zero. This allows loops to be created (such as for delays):

loop2     DECFSZ     test,f
              GOTO        loop2
              GOTO        Siren

and when the result is zero, the micro advances down the program to the instruction: GOTO        Siren
Do not use DECFSZ     test,w  if you want to decrement a file to zero (such as in a loop) as the instruction will only put the result of the decrement into w and the file will remain with its original value!

Special instructions
The PIC supports some special instructions which manipulate special PIC features. These are the CLRWDT, SLEEP, OPTION and TRISIO instructions.
Part of the reason why the PIC RISC core can be kept so simple is the rich set of Special Function Registers (SFRs). The PIC12F629 supports 16 SFRs, which are used to access special features. All of the SFRs are mapped into the PIC data space, and are accessed as if they were normal RAM data locations.
IND0 and FSR: This pair allow data memory to be indirectly accessed. The address of the data memory to be accessed is placed in the FSR.   FSR is file 04. The specified data memory can then be accessed as if it were in the IND0 register. The following code fragment may explain this better.
 
    MOVLW        10h            ; put value '10h'  into FSR
    MOVWF        FSR           ;
    MOVF           IND0,W      ;accessing INDO actually accesses data at address '10'

Indirect memory access is often useful for iterative (pronounced it'-ter-a-tive is an adjective meaning repetitious) operations such as reading or writing to buffers.
RTCC: The RTCC SFR gives access to the RTCC register mentioned above. This register may be read or modified.
PCL and PCLATH: These registers allow access to the low and high bytes of the current program counter (PC). The program counter holds the ad dress of the instruction which is currently being executed. Accessing the PC is not done commonly, except as a way to perform table look-ups or implement state machines.
Note that modifying the program counter invalidates the instruction pipeline. This means that an extra instruction cycle is required to load the next instruction.
STATUS: The status register holds the current arithmetic status, reset status and page preselector bits.
C is the carry/borrow bit. This bit is set if a carry out or borrow out occurred in the last arithmetic instruction (ADDWF, ADDLW, SUBWF, SUBLW). This bit is also modified by the rotate instructions (RLF and RRF).
DC is the digit carry/borrow bit. Its semantics (the way it works) are identical to C for arithmetic operations, except that it reflects a carry out or borrow out from bit 4 of the W register. This bit is not affected by rotate operations.
Z is the zero bit. This bit is set if the result of an arithmetic, logical or MOVF instruction is zero.
PD is the power-down bit. This is set to 1 during power-up or by a CLRWDT command. It is set to 0 by a SLEEP command.
TO is the time out bit. This is set to 1 during power up and by the CRLWDT and SLEEP commands. This bit is set to zero by a watchdog timeout.
The PD and TO bits may be used in conjunction to determine the cause of the last reset.
The PIC architecture supports 1024 bytes of data space (that is: 1024 lines of code or 1024 "instructions and table values etc").
RP1 and RP0 are the register page select bits for direct addressing of data space.
IRP should be maintained at 0.
The PIC12F629 supports the entire 1024 locations of the data space. This means a GOTO instruction can direct the micro to any part of the program.
OPTION: The option register controls some of the special functions available on the PIC devices. The OPTION instruction is used to load this register from the W register. By default all the bits are 1. The OPTION register is called OPTION_REG
PS2, PS1 and PS0 are the prescaler bits. These control the prescaler division rate. PSA is the prescaler assignment bit. This assigns the prescaler to the TIMER (timer0) if PSA=0. If PSA=1 it assigns the prescaler to the watchdog timer (WDT).
RTE controls the RTCC signal edge. The RTCC will increment on a low to high transition if this bit is zero, otherwise the RTCC will increment on a high to low transition. This is only useful if the RTS bit is set.
RTS selects the RTCC signal source. The RTCC will increment on internal clock transitions if this bit is zero, other wise the RTCC will increment on transitions of the RTCC pin.

INTEDG selects interrupt edge sensitivity of the INT pin (GPIO2). The interrupt will occur on falling edges (high to low transitions) if this bit is 1, other wise the interrupts will occur on rising edges (low to high transitions).
GPPU enables the weak pull-ups on GPIO pins when this bit is set to zero, otherwise the pull-ups are disabled. The pull-ups are disabled by default.

INTCON: This register controls which interrupts are enabled and identifies which interrupts have occurred. The interrupt mechanism is very flexible, to allow it to be tuned to react only to specific events.
GPIF is the GPIO interrupt flag. This is set when any of the GPIO input pins change. This flag must be reset in software.
INTF is the interrupt flag. This is set when the GP2/INT interrupt occurs. This flag must be reset in software.
T0IF is the Timer0 overflow interrupt flag. This is set when Timer0  overflows. This flag must be reset in software.
GIE is the global interrupt enable flag. If this flag is zero then no interrupts are enabled, otherwise the interrupts specified.
GPIO and TRISIO: These control access to the 12F629's six I/O pins. All of these pins can be used as inputs and all can be used as output except GP3 (pin4) which is input only. The TRISIO register controls whether the pins in GPIO are input or output. The TRISIO register can be set just like any other register, providing you access it in Bank 1. All output have a push-pull output drivers. GPIO2 has a Schmitt trigger input which gives a better noise immunity than the standard TTL level inputs of the other inputs.
All inputs have 'weak' pull-ups (typically 100uA - 47k). The weak pull-up is only active while the pin is in input mode and only if enabled by the RBPU bit in the OPTION register.
A word of caution. The actual write to an I/O pin only happens at the end of an instruction cycle, but the input state is latched at the beginning of a read operation. If a read instruction follows a write instruction, it is suggested that at least one instruction be inserted between the write and read, to allow the pin voltage to stabilise for the read operation.
EEDATA, EEADR, EECON1 and EECON2: These four registers control access to the 128 bytes of EEPROM data on the 12F629. EEDATA and EEADR work in a similar fashion to the IND0 and FSR pair. The address of the byte to be accessed is written into the EEADR register; the data at that address can then be accessed via the EEDATA register. This is relatively straightforward for reading the data, but writing the EEDATA is a bit more complex.

An EEPROM write cycle is a lengthy affair, taking up to 10 milliseconds. The WR bit in the EECON1 register is cleared by the EEPROM programming logic when the write cycle completes. The programming logic may also be configured to generate an interrupt on completion of the write cycle.
The EECON1 register is used to access the EEPROM control logic. It has the following five bits.
RD is the read control bit. Setting RD to 1 initiates an EEPROM read. This bit is cleared after a read by hardware and can not be cleared in software. A read takes one clock cycle.
WR is the write control bit. The EEPROM write cycle is initiated by per forming a fixed sequence of accessing EECON2 then setting WR to 1. WR is cleared by hardware when the write cycle has completed and, like the RD bit, cannot be cleared in software. As mentioned above, the write operation takes about 10 milliseconds.

WREN is the EEPROM write enable bit. All writes to EEPROM are inhibited when this bit is zero, otherwise they are allowed.
WRERR is the write error flag. This bit is set if a reset occurs and prevents the write operation from completing.
EEIF is the EEPROM write completion interrupt flag. This is set when a write cycle completes. This will generate an interrupt if enabled by the EEIE bit in the INTCON register.
EECON2 is not a physical register and is only used for performing part of the write sequence.

Configuration word
The configuration word controls the PIC's hardware features and is not a register or part of the program instruction space. It is not accessible at runtime, but can be accessed by the programmer. The following functions are supported.
FOSC2, FOSC1  and FOSC0 are used to select the oscillator type. By default, the RC oscillator is configured.
WDTE enables the watchdog timer feature. This is the only way to control the watchdog timer. In particular, the watchdog timer cannot be disabled by software. The watchdog timer is enabled by default.
PWRTE is the power-up timer enable fuse. This controls the operation of the power-up reset circuitry. This is enabled by default.
CP is the code protection fuse.
If code protection is enabled, reading the PIC will not produce any meaningful output and the program cannot be over written. This prevents unauthorised duplication of the program.
This fuse also serves two extra purposes in the 12F629. Firstly, it also prevents the EEPROM data from being accessed from the programmer. Secondly, it provides a mechanism for erasing the EEPROM data and program.
The configuration word is created by placing "CONFIG" in the first or second column and putting a double underbar in front: __CONFIG    In the next column is placed a number of features that are required to be implemented by the micro, such as code-protection on or off, watchdog timer on or off etc. Here is a typical __config with 4 features (more are normally required)

    __CONFIG   _CP_OFF & _WDT_OFF & _PWRTE_ON & _INTRC_OSC_NOCLKOUT